Topic Finder for Chapter 3
Introduction
Countings
The 74161 CLOCK Input
The 74161CLEAR Input
The Race Condition
The Load Input
The Enable Inputs
Active Logic Labels with
Counters
Active Low Electrical Signals
Chapter 3 Overview
Review Questions
List of Figures
Figure 3.1 Pinout for 74161
Four Bit Binary Counter
Figure 3.2 74161 Counter
Circuit with LED Outputs
Figure 3.3 Count Sequence
for 74161
Figure 3.4 74161 Counter
Circuit to Automatically reset counter at 5th Pulse
Problem 3.11
Devices that have the ability to count are very important elements in automatic process control circuits. If, for example, the engineer's goal is to develop a control circuit that adds ingredients, brews, fills, and inventories 24,000 bottles of "Best Belch", a popular beer on most college campuses, it makes little sense to even attempt the task if there is no way to count the number of bottles. Unfortunately, like logical thinking, counting is a skill not really understood and often taken for granted by new engineering students.
Table 4 shows four popular ways to count. Counting in Base 2 is shown on the left. In this example 20 events were tallied. The same number of events were recorded in Base 8, Base 10 and Base 16. If an engineer has any aspirations with respect to learning how to create digital control circuits or deal with computers at any level beyond a menu driven program user, than Table 4 should be studied until it is mastered. At that point Table 5 and Table 6 can be easily filled in on your own. It is important to study Table 4 until Table 5 and Table 6 do not pose any problems. After all it is only counting and, if all else fails, we can always use our fingers, toes and nose
One example of a nonhuman device that counts is the 74161 TTL device. Figure 3.1 provides a pin out for this chip. Figure 3.2 shows a circuit diagram of a simple circuit that, if built correctly, will illustrate how the 74161 performs. (A function diagram of that circuit would not have to include all of the pin connection details. In addition, the 74161 label might be replaced with just the word "counter".) There are several user friendly features incorporated into the 74161. These are associated with pins on the device and are identified by the words Clock, Clear, Load and Enable. These functions are now described with some detail.
The word CLOCK and the clock action are associated with pin 2 of the 74161. If a square wave signal, i.e. a signal that starts at one level goes to a different level and then returns to its original level, is applied to pin 2 then this signal is called a clock pulse. The clock pulses delivered to a clock pin on the 74161 will, under certain conditions, make the 74161 generate specific but sequential high and low signal patterns on output pins 14, 13, 12 and 11.
When examining the output voltages of the 74161 it is most convenient to look at all four output pins as a single written pattern of four possible voltage values. The individual voltage values should be written on the paper so that the voltage on pin 11 is on the left side of this horizontally arranged pattern. Thus the outputs would be written from left to right as voltage values from pin 11, pin 12, pin 13 and finally pin 14 on the right.
It is also important to get into the habit of reading the voltage output values from this or any other counter as a set of ones and zeros that start at the right and go to the left. Thus the first voltage read and spoken is the value on pin 14 while the last voltage read is the voltage on pin 11. This is a good practice because it always put the least significant bit, LSB, on the right and the most significant bit, MSB, on the left.
Figure 3.3 illustrates three different clock pulse situations associated with an abbreviated drawing of the circuit shown in Figure 3.2. Figure 3.3A shows the current status of the counter after a clock pulse labeled "a" has reached pin 2 on the 74161. The figure also suggests that 2 separate additional pulses are traveling down a wire and will soon arrive at pin 2. For now, since pulse "b" has not reached pin 2, the 74161 output voltage pattern represented on pins 11, 12, 13 and 14 is 0V, 5V, 5V and 5V. Figure 3.3B illustrates the change in the 74161 output pins after pulse "b" has reached pin 2 on the 74161. As the drawing suggests pulse "c" is still on the wire and has moved closer to but has not reached pin 2. Under these circumstances the four output pins, pins 11, 12, 13 and 14, are generating 5V, 0V, 0V and 0V signals, respectively.
Finally, Figure 3.3C gives the status of the chip after pulse"c" has arrived at pin 2. The drawing indicates no additional square waves approaching the 74161. Output pins 11, 12, 13 and 14 now have 5V, 0V, 0V and 5V signals. Thus the output pin pattern changes that the 74161 generated are a result of the arrival of pulses "a", "b" and "c" at its clock pin. Table 7 shows these results. Review of this table, together with the counting numbers summary in Table 4, should make it clear why it is more appropriate to label these pulses as pulse #7, pulse #8 and pulse #9. Please convince yourself of this fact.
Table
8 illustrates an interesting point and suggests another.
After 16 additional pulses the 74161 has an output pattern associated with
the number 9. The table also suggests that if there had been 17 additional
pulses instead of 16 then the pattern presented by the counter would have
again been the first pattern in
Table 8. All counters behave in a similar fashion.
As clock pulses arrive at the clock pin the chip responds by altering the
output pattern in a predictable sequence. The number of patterns
that are generated before the counter recycles depends on the number of
its output pins. A counter with just one output pin can generate
two patterns, 0 and 1. A counter with two output pins can generate
four patterns, 00,01,10 and 11. A counter with four output pins can generate
16 patterns, see Table 8.
As may be expected from these examples, the number of patterns is 2 raised
to the nth power, where n is the number of output pins.
The sequence of patterns shown in Table 8 will have little value if there is no way to assure that the counter will begin to generate patterns at a predictable starting point in the sequence. The CLEAR function, pin 1, provides this guarantee. A review of Figure 3.2 indicates that there is a push button, PB1, attached to the CLEAR pin. If no human action is taken with respect to PB1, then the signal delivered to pin 1 shown in Figure 3.2 is at 5V. If the button is pushed then 0V is supplied to pin 1. When the button is released then the voltage at the CLEAR pin returns to 5V. This button action generates a square wave at pin 1 and this transition through 0V is detected by the 74161 which immediately returns, resets, all of its output pins to 0V. Thus, the counter's output pattern returns to zero, i.e 0V, 0V, 0V and 0V on pins 11, 12, 13 and 14, respectively whenever 0V is applied to the CLEAR pin of the 74161. If pin 1 in Figure 3.2 is held at 0V, then, no matter how many clock pulses arrive at pin 2, the counter will still display the pattern 0V, 0V, 0V and 0V on its output pins. Thus the counter remains in its clear mode. The number 010, as represented by the binary zeros on the counter's output pins, stays as long as pin 1 is at 0V. The counter is said to be cleared.
A common action for a control circuit that uses the 74161 or any other digital counter is to clear, reset, the counter to zero before any new sequence of event counting is to be initiated. As suggested above, this might be accomplished by a human pushing a button. More likely the counter is cleared by the output from another digital circuit that momentarily supplies 0V to the CLEAR pin. A NOR logic device is often employed for this purpose. Its output wire is connected to the counter's Clear pin. Once this is done the counter will reset to zero whenever either input to the NOR is raised to 5 volts.
Figure 3.4 illustrates a simple but crude example of this clear strategy. In this example, a NAND is used instead of a NOR. The counter outputs are connected to a LED display unit. In addition, two of the outputs, pin 12 and pin 14 are also connected to the inputs of a 7400 NAND device. The output of the NAND is returned to the CLEAR input of the 74161. This NAND feedback loop allows the counter to be reset to zero once the count pattern reaches 5. At that point, the NAND senses 5 volts at its inputs and responds with a 0V signal on its output. The logic 0 supplied by the NAND puts the 74161 CLEAR pin low,(0V), forcing the output pattern of the 74161 to 0 0 0 0. The cleared counter output pattern shows on the LED display circuit as the number 0 and the inputs of the NAND device both return to 0 volts.
With all of these new conditions in place, the NAND output state changes from logic 0 to logic 1 which, in turn, releases the 74161 CLEAR pin. This permits the next clock pulse at pin 1 to be recorded as the first event of the new event cycle. Now additional clock pulses at the 74161 clock pin will force the 74161 outputs to sequentially produce binary patterns that represent the numbers from 1 to 4. Upon the arrival of the fifth clock pulse the 74161 CLEAR function is activated again and the counter output returns to zero. You should note that the count goes from zero to four. What would happen if the circuit in Figure 3.4 were rewired so that counter output QB was connected to the NAND input instead of counter output QC? The count would go from zero to two. The reason for this behavior is discussed below.
The clear action suggested in Figure 3.4 is summarized in Table 9. Note that the counter output voltage pattern 0V, 5V, 0V, 5V although shown in the figure is not included in the summary. This was done to introduces the "race" concept. A race occurs in a digital circuit when two different results could happen depending on which signal or group of signals reaches its target first. In this situation the race is between the 74161 output voltage pattern reaching the LED display and the CLEAR pin detecting and acting upon the 0V signal from the NAND. When deciding the signal that will win a race it is necessary to consider the two important but different judgement perspective.
From an electronics perspective, it is clear that the number 5 on LED display is the winner. The LEDs detect the 0V,5V,0V,5V pattern at the same time the NAND notices the two 5V signals at its inputs. This has to be the case. The electrical signals travel so fast on the wires that any small travel distance difference from the counter outputs to the LED display and the counter outputs to the NAND input pins would not make any difference. Thus, the output pattern from the counter reaches the LED display and the inputs to the NAND device at the same time.
From the human eye or any other slow sensor's perspective, the CLEAR function on the 74161 is the winner. Although the total time it takes for the NAND to change its output signal from 5V to 0V plus the time it takes for the 74161 to detect and react to the NAND's 0V signal on its CLEAR pin is much longer than the time it takes for the LED display to detect the 0101 pattern and react by promptly displaying the number 5, the human eye is not quick enough to distinguish that amount of time. As a result, the eye never detects that the pattern for the number 5 did indeed show up on the display. On the other hand, the eye does see the results of the CLEAR action since the number zero on the LED display will stay visible as long as the four 74161 outputs remain at 0V, 0V, 0V and 0V. That is to say, the 0 on the display stays there until the next clock pulse arrives at pin 2 of the 74161. This was a trivial example of a race condition. Unfortunately race conditions can occur in many digital circuits and the results are usually not trivial. An engineer can spend a lot of time trying to trouble shoot a digital control circuit that has a race situation. The circuit seems to be correct on paper but it just does not seem to control the process correctly in practice. The best defense against a race condition is to avoid it. The best analysis tool to detect the existence of a race condition is to employ the two judgement perspective with the following conflicting rules of thumb.
a) "The signal path that has the least number of devices will lead to the winning device and the circuit will always initially behave as dictated by that device."
b) "The final behavior pattern of the circuit depends on the steady state actions of the device in the slow race path as well."
In the example outlined in Figure 3.4, it is true that the 0101 pattern reached the LED display first. It is also true that the number 5 did appear on the display first. However, in the final analysis, the number 5 will not remain on the display long enough for the human to see it because the longer, slower signal path through the NAND to the CLEAR pin produced a steady state signal that ultimately resets the counter. As a result, the counter removes the number 5 from the LED display inputs and replaces it with the number 0. In this case, this clear action was quicker than the eye can detect the five displayed in the first place and the number 0 remains long enough for the human to see it.
Figure 3.2 also illustrates two additional push buttons connected to input pins of the 74161. One of those pins is identified as the Load Input, pin 9. This input controls the operation of the Load function. The idea of the Load pin is straight forward. The 74161 has the ability to start counting at numbers other than zero. We have already introduced the idea of the Clear function and the addition concept that after the 74161 output pins are changed to 0 volts and the Clear pin is returned to 5 volts, the counter will respond to the next clock pulse by putting the pattern for the number 1 onto its output pins. The Load function just offers more degrees of freedom as to where the counter starts counting.
For the example illustrated in Figure 3.2, please notice that the voltage pattern on pins 6, 5, 4, and 3 is now set at 0V, 5V, 5V, and 5V, respectively. The idea associated with the LOAD pin is to transfer this voltage pattern for the number 7 from input pins D, C, B, and A to the corresponding 74161 output pins, QD, QC, QB, and QA. After this has been done, the next clock pulse on the clock pin will allow the counter to display the output pattern for the number 8, i.e. QD will be at 5V and the other output pins, QC, QB, and QA, will be at 0V.
The specific way to accomplish this Load operation is straight forward. As Figure 3.2 indicates, the current voltage on pin 9 is 5 volts. Once PB3 is pushed this pin goes to 0 volts and the 74161 will respond to the next clock pulse on pin 2 by moving the voltage pattern in the D, C, B, and A input pins to the corresponding output pins. (In this case, the clock pulse can be generated by pushing PB2 and then releasing it.) As long as PB3 is held down the counter output pins will always display the number 7. Once PB3 is released pin 9 returns to 5V and the 74161 will change the output pattern from a 7 to an 8 when it detects the next clock pulse on pin 2.
Perhaps the function of pin 10 and pin 7, the T and P Enable pins, should have been discussed first. In the example shown in Figure 3.2, these pins are at 5 volts, however Enable P is also attached to PB4. Under these enable pin conditions the counter will change the count value on the 74161 output pins every time a clock pulse arrives at pin 2. This statement is true only if the Load and Clear pins are at 5V. Assuming that the Clear and Load pins are at 5 volts the counter will continue to respond to clock inputs until either of the Enable pins is changed to 0 volts. For the example shown, the P Enable pin is at 5 volts because none is pushing PB4. If PB 4 is pushed, pin 7 goes from 5 volts to 0 volts and the counter will not respond to the next clock pulse on pin 2. No matter how many new clock pulses are delivered to pin 2, the count value on the 74161 output pins remain at its current value until PB4 is released and the voltage on pin 7 returns to 5 volts.
If PB4 had been attached to the T Enable pin in Figure 3.2 instead of the P Enable pin, the 74161 would count or not count depending on the voltage PB4 delivered to pin 10. This is true as long as pin 7 is at 5 volts. The role of the T Enable is identical to the role of the P Enable. The extra enable pin merely allows you to design a control system that has two different ways to stop the counter. A nice feature of the 74161 but perhaps not to be appreciated at this time.
Active Logic Labels with Counters
The use of the Active or Passive logic signal concept works not only with logic signals but with some of the functions in counters. Reexamine the 74161 pinout shown in Figure 3.1. Pin 1 is the CLEAR pin and if that pin is at logic zero the outputs of the counter will all be at logic zero. One way to restate that idea is to simply say
The CLEAR function on the 74161 is active when it is at Logic zero.
Of course, the meaning of CLEAR has to be memorized However, CLEAR always means that the output or outputs of the device are brought to logic zero. For practice, try your skill at describing pin 9 on Figure 3.1. Please note that the idea of an active logic signal does is not used with pins 14,13,12 and 11. These are the counter output pins and there job is to provide a predictable pattern each time the 74161 detects a CLOCK pulse. Hopefully you already know what those patterns are. For example, if the current output on a 74161 is 0 on QD, 1 on QC, 0 on QB and 1 on QA, you already know the next pattern that will appear on these outputs because of the next CLOCK pulse. Please review Table 8, if that is not the case.
There is one additional idea that is attached to this Active Logic Signal concept. At this point, only the word Active or Passive has been used. The example presented at the end of the Introduction chapter was about a temperature sensor and a pressure sensor that controlled the position of a valve. If the temperature was to high or the pressure was to low then the valve was to open. The simple statement of that control ideal was
When the TSH OR the PSL are active the valve is active.
On review of this statement, it should be obvious that there was no mention of which logic signal was the active signal. Of course, there may have been a temptation to make an assumption but since there are two possible electrical signal values, the high value and the low value, there is only a 50% chance that the assumption was correct. There is a specific way to indicate what electrical signal level is required to make an input pin of a digital device active. There is a specific way to indicate what electrical signal level is delivered by the output pin of a digital device when that pin is active. Consider a few examples:
The CLEAR function on
the 74161 is an Active Low function and the outputs of the counter
will be cleared if the
CLEAR pin is at the
low electrical signal.
Now consider the ENABLE pins on the same
device. The P ENABLE pin on the 74161 is an active high input. This
means that the 74161 will not perform its counting
function unless the P ENABLE pin is at the high electrical signal.
This is also the case for the T ENABLE pin
on the 74161.
An easy way to state these facts is as follows.
The 74161 CLEAR pin is an Active Low Input. The P ENABLE pin is an Active High Input. The T ENABLE pin is an Active High Input.
Thus adding the descriptors Low (High) to the active state, allows the reader not only to know why an input pin is to be made active but now to know how to make that desired pin active.
In summary, the term active (passive) is used to
predict what logic will happen because of the status of the sensors in
the control scheme. The term high (low) is used to specifically indicate
the exact electrical signal needed to make the digital device input active
or the exact electrical signal that will be delivered an active digital
device output pin. Please note the line drawn over the CLEAR pin
in Figure 3.1
but the absence of that line on the P ENABLE and T ENABLE
pins.
Chapter 3 Overview
3. 1 What are the entries for the next row of Table 4?
3. 2 What are the entries for the third row of Table 5?
3. 3 Examine Figure 3.1. What happens if pin 9 is low and a clock pulse arrives at pin 2?
3. 4 Examine Figure 3.2. What happens if;
a) the push button attached to pin 2, PB2, is pushed and released while PB1 is held down?
b) PB3 is held down while PB2 is pushed and released?
c) PB4 is held down while PB2 is pushed and released?
d) any of the push buttons is pushed while PB2 is held down?
3. 5 What is the output pattern for the next row of Table 8?
3. 6 What would the output pattern be if one more pulse arrived at the clock pin of the 74161 in Figure 3.3?
3. 7 Examine Figure 3.4.
Assuming the count was initially cleared, what is the pattern on the LED's
when the sixth pulse is
detected by the clock pin?
3. 8 What are the entries for the next row of Table 9?
3. 9 What is the reason for your answer to Question 3.8?
3.10 Use the 74161 and only one additional TTL Package, show the function diagram of a circuit that would inhabit the counter when the counter senses a stop signal from either of two separate STOP push buttons. (NOTE that a stop signal is always a square wave that starts at 5 volts before the button is pushed. Goes to 0 volts when the button is pushed and then returns to 5 volts after the button is released.)((THIS PROBLEM WILL BE ON THE SECOND TEST))
3.11 Examine the Figure and answer the questions.